The present disclosure relates generally to a computer implemented method for managing an interruption while a processor is in a transactional execution (TX) mode executing a transaction.
The number of central processing unit (CPU) cores on a chip and the number of CPU cores connected to a shared memory continues to grow significantly to support growing workload capacity demand. The increasing number of CPUs cooperating to process the same workloads puts a significant burden on software scalability; for example, shared queues or data-structures protected by traditional semaphores become hot spots and lead to sub-linear n-way scaling curves. Traditionally this has been countered by implementing finer-grained locking in software, and with lower latency/higher bandwidth interconnects in hardware. Implementing fine-grained locking to improve software scalability can be very complicated and error-prone, and at today's CPU frequencies, the latencies of hardware interconnects are limited by the physical dimension of the chips and systems, and by the speed of light.
Implementations of hardware transactional memory (HTM, or in this discussion, simply TM) have been introduced, wherein a group of instructions—called a transaction—operate in an atomic manner on a data structure in memory, as viewed by other central processing units (CPUs) and the I/O subsystem (atomic operation is also known as block concurrent or serialized in other literature). The transaction executes optimistically without obtaining a lock, but may need to abort and retry the transaction execution if an operation, of the executing transaction, on a memory location conflicts with anther operation on the same memory location. Previously, software transactional memory implementations have been proposed to support software Transactional Memory (STM). However, hardware TM can provide improved performance aspects and ease of use over software TM.
Commonly owned U.S. Pat. No. 6,381,606 titled “Application Programming Interface for Creating Authorized Connections to a Database Management System”, filed Jun. 28, 1999, is incorporated by reference, and teaches a method, apparatus, and article of manufacture for accessing a database management system. An application programming interface (API) provides a plurality of simplified procedures that allow an application program executed by the computer to access a database management system (DBMS) by creating an authorized connection between the application program and the DBMS. The application program invokes the simplified procedures of the API, the invoked procedures generate at least one supervisor call (SVC) interrupt that transfers control to an SVC Service Routine, and the SVC Service Routine connects to a Cross Coupling Facility (XCF) that interfaces to an Open Transaction Manager Access (OTMA) component of the DBMS.
Commonly owned U.S. Pat. No. 5,715,458 titled “Incorporation of Services Written in one Operating System Environment into Another Operating System Environment”, filed Feb. 13, 1995, is incorporated by reference, and teaches a data processing apparatus which comprises a processor and memory. The processor has a supervisor state including a first set of supervisor service routines for controlling the operation of the data processing apparatus. The memory has a first hash table accessible by the supervisor state for pointing to the first set of supervisor service routines and a second hash table also accessible by the supervisor state for pointing to a second set of supervisor service routines. The data processing apparatus provides table indicating means for indicating whether the first hash table or the second hash table is accessible by the supervisor state. The table indicating means is provided as an index into the first hash table. When this index is accessed, further code is executed which allows access to the second hash table. The operation of the data processing apparatus is controlled by a routine comprising the steps of testing to determine which hash table is to be used for calling the routine, using the determined hash table to find the address in the memory at which the code representing the called routine is resident, and executing the routine in the processor. In one embodiment of the '458 disclosure, the first step comprises testing the operating system environment in the processor. The '458 disclosure finds particular use in providing in a first operating system environment, such as MVS/ESA™, services written for a second operating system environment, such as VSE/ESA™.